A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock

A low power architecture to extend the frequency range of quadrature clock is proposed. This architecture is based on a series of dividers. It can enhance the lower frequency limit of a Quadrature Voltage Controlled Oscillator (QVCO) clock to any arbitrarily small frequency. Based on the architecture a design is shown which enhances the low frequency range up to -90% of the center frequency, assuming the QVCO tuning range is +20%. The dividers are made of Dynamic Transmission Gate Logic (DTGL) to reduce power consumption. Simulation result shows that the power consumption of the extender circuit, excluding the QVCO, is 2.1 mW from 1.2 V supply voltage at 3 GHz input frequency in 90 nm CMOS technology. The output jitter contribution by this circuit is 2 ps and 0.15 ps for mismatch and thermal noise respectively. Maximum output frequency achieved is 4.8 GHz for differential clock and 2.4 GHz for quadrature clock.