DocumentCode
2366269
Title
Cryogenic operation of static induction (SIT/SITh) devices
Author
Singh, Ranbir ; Baliga, B.J.
Author_Institution
Power Semicond. Res. Center, North Carolina State Univ., Raleigh, NC, USA
fYear
1995
fDate
23-25 May 1995
Firstpage
267
Lastpage
272
Abstract
Detailed measurements and modeling of a 200 V, n-channel SIT with a vertically walled gate structure and a 500 V, asymmetrical planar gate SITh in the 300 to 77 K temperature range are described for the first time. When the temperature is reduced from 300 to 77 K, it has been observed that: maximum blocking voltage in these devices decreases by 20%; DC blocking gain increases slightly, a 7.5× reduction in forward drop occurs for the SIT while a 40% increase in the knee voltage and a dramatically improved I-V slope occurs at high current densities for the SITh; and during gate turn off of the SITh, a 95× and 10× reduction in extracted gate charge and turn off time occurs, respectively. The SITh forward drop vs turn off time trade off curve obtained by temperature reduction is much superior to that obtained by electron radiation
Keywords
cryogenic electronics; power field effect transistors; static induction transistors; thyristors; 200 V; 500 V; 77 to 300 K; DC blocking gain; I-V slope; asymmetrical planar gate static induction thyristor; blocking voltage; cryogenic operation; current density; electron radiation; forward drop; gate charge; knee voltage; n-channel static induction transistor; turn off time; vertically walled gate; Cryogenics; Electrons; FETs; Frequency; High temperature superconductors; JFETs; Temperature distribution; Thyristors; Time measurement; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices and ICs, 1995. ISPSD '95., Proceedings of the 7th International Symposium on
Conference_Location
Yokohama
ISSN
1063-6854
Print_ISBN
0-7803-2618-0
Type
conf
DOI
10.1109/ISPSD.1995.515047
Filename
515047
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