On-Chip Air-Gap Fabrication Using A New Sacrificial Polymer for Ultra Low-k Dielectrics

As the minimum feature size of integrated circuits decreases, the need for ultra low-k dielectrics with copper metal increasing in order to reduce the RC delay, energy dissipation, and cross talk caused by the copper interconnects. The ITRS presents a goal for the effective dielectric constant for the 45 nm node at 2.3-2.6. Previous work has shown that intra-level air-gaps provide a very low effective dielectric constant reducing the propagation times and lowering the crosstalk. Air-gaps are most effective in local interconnect levels due to the small pitch and dense interconnect structures. In this study, the fabrication processes for forming air-gaps using a sacrificial polymer is presented. In addition, methods for extending the air-gap into the inter-level dielectric region further lowering the effective dielectric constant, is presented. The critical processing issues for integration of sacrificial material into the intra-level damascene process are presented. Modeling has been used to evaluate the benefits of the intra-level air-gap, extension of the air-gap into the inter-level dielectric, and effect of a low-k inter-level dielectric. Advanced sacrificial polymers were used to fabrication the air-gap structures. Test structures are being fabricated to verify the processing methods and benefits of air isolation. High aspect ratio air-gaps are most effective in lowering the overall capacitance. The half pitch of air-gap interconnect structure being fabricated is 200 nm and the aspect ratio (height-to-width) is 2.0. Based on the modeling, an effective dielectric constant of than 2.0 is feasible