Influence of parasitic capacitances on switching characteristics of SOI-LDMOSs

Author

Suzuki, Yuji ; Leung, Ying-Keung ; Wong, S. Simon

Author_Institution

Central Res. Lab., Matsushita Electr. Works Ltd., Osaka, Japan

fYear

1995

fDate

23-25 May 1995

Firstpage

303

Lastpage

308

Abstract

This paper describes the influence of parasitic capacitances on the switching characteristics of lateral DMOSFETs fabricated in Silicon on Insulator (SOI) substrates with silicon thicknesses from 1 to 20 μm. The dependences of the parasitic capacitances, especially an additional drain-substrate capacitance attributed to the use of an SOI substrate, on the drift region length, silicon layer thickness and buried oxide thickness are confirmed experimentally. It is shown that optimization of these parameters is critical for high speed switching applications

Keywords

MOS integrated circuits; buried layers; capacitance; electric breakdown; field effect transistor switches; isolation technology; power MOSFET; power field effect transistors; power integrated circuits; power semiconductor switches; silicon-on-insulator; 1 to 20 micron; SOI substrates; SOI-LDMOSs; Si; Si layer thickness; buried oxide thickness; drain-substrate capacitance; drift region length; high speed switching applications; lateral DMOSFETs; parasitic capacitances; switching characteristics; Capacitance-voltage characteristics; Dielectric devices; Dielectric substrates; Doping; FETs; Isolation technology; Laboratories; MOSFETs; Parasitic capacitance; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1995. ISPSD '95., Proceedings of the 7th International Symposium on

Conference_Location

Yokohama

ISSN

1063-6854

Print_ISBN

0-7803-2618-0

Type

conf

DOI

10.1109/ISPSD.1995.515054

Filename

515054