Run-Time Reconfigurable Hardware-Software Architecture for PID Motor Control IP Cores

The flexibility of the system-on-a-programmable-chips (SoPCs) in motor multi-axis control systems, makes possible the processing of the most intensive computation operations by hardware (PID IP Cores) and the trajectory computation by software. Usually the trajectory generation software runs in powerful FPGA embedded microprocessors. However, these SoPC systems, with many buses and distributed architecture, may lack flexibility for fast intelligent response against some events, e.g. in an emergency motor stop. In this paper, we present a new architecture for PID motor control IP cores that embeds a tiny soft processor that can track locally the PID section of the core for an specific simple trajectory independently of the central SoPC microprocessor. Additionally, the software and the control constants can be fast replaced using dynamic partial reconfiguration. We evaluate the implementation results of one core designed with this architecture and its integration in a multi-axis control SoPC