• DocumentCode
    2366503
  • Title

    SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

  • Author

    Wang, Weixun ; Mishra, Prabhat ; Gordon-Ross, Ann

  • Author_Institution
    Dept. of Comput. & Inf. Sci. & Eng., Univ. of Florida, Gainesville, FL
  • fYear
    2009
  • fDate
    5-9 Jan. 2009
  • Firstpage
    547
  • Lastpage
    552
  • Abstract
    Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well as for improving overall system performance. It is a major challenge to introduce cache reconfiguration into real-time embedded systems since dynamic analysis may adversely affect tasks with real-time constraints. This paper presents a novel approach for implementing cache reconfiguration in soft real-time systems by efficiently leveraging static analysis during execution to both minimize energy and maximize performance. To the best of our knowledge, this is the first attempt to integrate dynamic cache reconfiguration in real-time scheduling techniques. Our experimental results using a wide variety of applications have demonstrated that our approach can significantly (up to 74%) reduce the overall energy consumption of the cache hierarchy in soft real-time systems.
  • Keywords
    cache storage; dynamic scheduling; embedded systems; multiprocessing systems; optimisation; processor scheduling; reconfigurable architectures; cache hierarchy; dynamic cache reconfiguration; energy consumption; real-time embedded systems; real-time scheduling techniques; scheduling-aware cache reconfiguration; Design optimization; Dynamic scheduling; Embedded computing; Embedded system; Energy consumption; Performance analysis; Processor scheduling; Real time systems; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2009 22nd International Conference on
  • Conference_Location
    New Delhi
  • ISSN
    1063-9667
  • Print_ISBN
    978-0-7695-3506-7
  • Type

    conf

  • DOI
    10.1109/VLSI.Design.2009.66
  • Filename
    4749729