DocumentCode
2366575
Title
Testing nanometer digital integrated circuits: myths, reality and the road ahead
Author
Blanton, Shawn ; Mitra, Subhasish
Author_Institution
Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
2005
fDate
3-7 Jan. 2005
Firstpage
8
Lastpage
9
Abstract
High-test quality plays a central role in the development of successful products used for building robust computing and communication systems. Hence, high-test quality enablers are rapidly becoming "features", just like performance, power-consumption and die size. This tutorial includes in-depth discussions on two major test topics that are essential for designs manufactured in nanometer technologies: test compression and diagnosis. Test compression techniques enable orders of magnitude improvement (reduction) in test cost and pave the path for successful implementation of built-in-self-test features. Ensuring products yield with sufficient quality also requires techniques for identifying and characterizing defects. This tutorial describes state-of-the-art techniques for performing defect diagnosis and how such techniques are key in enabling high-yielding and high-quality products. Supporting data from actual designs and manufacturing processes are presented.
Keywords
built-in self test; fault diagnosis; integrated circuit testing; integrated circuit yield; logic testing; nanoelectronics; built-in-self-test features; defect diagnosis; high-test quality; magnitude improvement; manufacturing processes; nanometer digital integrated circuit testing; nanometer technology; test compression; test cost reduction; Automatic testing; Circuit testing; Digital integrated circuits; Integrated circuit testing; Manufacturing; Micromechanical devices; Roads; Robustness; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2005. 18th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2264-5
Type
conf
DOI
10.1109/ICVD.2005.162
Filename
1383236
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