• DocumentCode
    2366615
  • Title

    Test methodologies in the deep submicron era - analog, mixed-signal and RF

  • Author

    Chatterjee, A. ; Keshavarzi, A. ; Patra, A. ; Mukhopadhyay, S.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    2005
  • fDate
    3-7 Jan. 2005
  • Firstpage
    12
  • Lastpage
    13
  • Abstract
    Summary form only given. The goal of this tutorial is to give the audience a detailed overview of testing challenges, proposed solutions and open problems. The tutorial starts with the introduction to testing challenges in the deep sub micron era. Issues with process variations and leakage and their impact on testing are discussed. This is followed by issues regarding fault modeling, DFT and BIST of analog and mixed signal circuits. It is shown how behavioral modeling could be utilized for such circuits in, conceptually, the same way that stuck-at fault modeling is used for digital testing. Issues and conceptual details regarding on-line testing are introduced, both in the contexts of digital as well as mixed signal circuits. The last part of the tutorial introduces in detail concept of built-in test (BIT) and built-off self-test (BOST) for high frequency RF circuits. A new paradigm for BIST of high-speed/RF circuits using alternate tests is also introduced.
  • Keywords
    VLSI; analogue integrated circuits; built-in self test; circuit analysis computing; design for testability; fault simulation; integrated circuit testing; mixed analogue-digital integrated circuits; radiofrequency integrated circuits; analog circuits; behavioral modeling; built-in self test; built-off self-test; circuit testing; high frequency RF circuits; mixed-signal circuits; online testing; stuck-at fault modeling; technology scaling; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Electronic equipment testing; Laboratories; Microprocessors; Radio frequency; System testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2005. 18th International Conference on
  • Conference_Location
    Kolkata, India
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2264-5
  • Type

    conf

  • DOI
    10.1109/ICVD.2005.161
  • Filename
    1383238