Title :
Improving the parallelism and concurrency in decoupled architectures
Author :
John, L. ; Radhakrisnan, R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
Concurrency between access and execution has been exploited by queues in many decoupled access-execute architectures, but data dependent control dependencies often prohibit prefetching of data to queues. This paper investigates a technique to facilitate anticipatory loading to queues even in presence of data dependent control dependencies. The proposed method consists of fetching along one or both paths of a data dependent control dependency and inserting consume instructions in appropriate paths to consume the unnecessarily fetched data. The compiler hoists load instructions above control dependencies as in conventional load hoisting techniques. The technique is seen to be very effective in programs with data dependent if-then-else´s. We also present an architecture with multiple access units, the mLSU architecture, which parallelizes the access process. Simulation experiments illustrate that multiple access units improve the performance if access processor instruction issue is a bottleneck
Keywords :
parallel architectures; processor scheduling; program compilers; anticipatory loading; compiler; concurrency; data dependent control dependency; decoupled architectures; load instructions; mLSU architecture; multiple access units; parallelism; Buffer storage; Computer aided instruction; Computer applications; Computer architecture; Concurrent computing; Dynamic scheduling; Parallel processing; Pipelines; Prefetching; Processor scheduling;
Conference_Titel :
Parallel and Distributed Processing, 1996., Eighth IEEE Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
0-8186-7683-3
DOI :
10.1109/SPDP.1996.570325