DocumentCode
2366920
Title
Top-down lower bounds for depth 3 circuits
Author
Håstad, J. ; Jukna, S. ; Pudlák, P.
Author_Institution
Dept. of Comput. Sci., R. Inst. of Technol., Stockholm, Sweden
fYear
1993
fDate
3-5 Nov 1993
Firstpage
124
Lastpage
129
Abstract
We present a top-down lower bound method for depth 3 AND-OR-NOT circuits which is simpler than the previous methods and in some cases gives better lower bounds. In particular we prove that depth 3 AND-OR-NOT circuits that compute PARITY resp. MAJORITY require size at least 20.618...√n resp. 20.849...√n. This is the first simple proof of a strong lower bound by a top-down argument for non-monotone circuits
Keywords
Boolean functions; computational complexity; logic circuits; depth 3 AND-OR-NOT circuits; depth 3 circuits; nonmonotone circuits; strong lower bound; top-down argument; top-down lower bounds; Boolean functions; Circuit analysis; Combinatorial mathematics; Computational modeling; Computer science; Costs; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Foundations of Computer Science, 1993. Proceedings., 34th Annual Symposium on
Conference_Location
Palo Alto, CA
Print_ISBN
0-8186-4370-6
Type
conf
DOI
10.1109/SFCS.1993.366875
Filename
366875
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