Abstract :
Summary form only given. Transactors, also known as bus-functional models, have traditionally been modeled using a procedural interface (API). Commands were provided to use every feature available in the transactor. Several commands were often necessary to configure the transactor or to execute the simplest transaction. If the transactor did not provide a feature required by a particular device under test (DUT) or testcase, it had to be modified or rewritten. By using an object-oriented approach for configuration and interfacing, transactors can easily be used out-of-the-box. A few lines are all that is necessary to create valid random stimulus to a DUT or report observed response to a scoreboard. The use of callback methods eliminates the need for a complex and ever-evolving API. Instead of creating yet-another programming language, it leverages the power of system Verilog to extend the functionality of a transactor in ways the original author may not have conceived. Without modification, a transactor can thus be used and reused effectively. Transactors can also be modeled in an extensible fashion. Extensible transactors allow users to define entirely new transactions and commands, should the ones provided by the original implementation prove insufficient. Usability and reusability of transactors does not happen by accident. With careful design and consistent use model, transactors can be written to meet the stringent demands of different testcases on different design under verification. This paper describes how to properly use the object-oriented features of system Verilog to model transactions and transactors that execute them. Designers, used to a procedural programming model, will learn how to approach a transactor modeling problem using the object-oriented approach. Software engineers, used to a traditional object-oriented programming model, will learn how to adapt their methods to the special requirements of constrained-random verification. This paper presents clear and concise guidelines that can be followed to create effective, easy-to-use and reusable transactor models.
Keywords :
application program interfaces; formal verification; hardware description languages; object-oriented methods; transaction processing; callback methods; constrained-random verification; design under verification; device under test; object-oriented approach; object-oriented features; procedural programming model; reusable transactor models; system Verilog; transactor functionality; transactor modeling problem; usable transactors; Computer languages; Guidelines; Hardware design languages; Industrial training; Object oriented modeling; Object oriented programming; Power system modeling; Testing; Usability; Writing;