Title :
EOS/ESD analysis of high-density logic chips
Author :
Ramaswamy, S. ; Duvvury, C. ; Amerasekera, A. ; Reddy, V. ; Kang, S.M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
Electrical overstress (EOS) and electrostatic discharge (ESD) are a major cause for field failures in integrated circuits. Effective design of I/O protection circuits is important to achieve overall EOS/ESD reliability. A wide range of CMOS applications is leading to IC chips with different on-chip capacitance values. Using experimental methods combined with device/circuit simulators, we show the important role of chip capacitance on effective I/O protection design.
Keywords :
CMOS logic circuits; electrostatic discharge; CMOS integrated circuit; EOS; ESD; I/O protection circuit; chip capacitance; design; device simulator; electrical overstress; electrostatic discharge; field failure; high-density logic chip; reliability; CMOSFET logic devices; Electrostatic discharges;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 1996. Proceedings
Print_ISBN :
1-878303-69-4
DOI :
10.1109/EOSESD.1996.865155
