A compact model for the grounded-gate nMOS behaviour under CDM ESD stress

Author

Russ, Christian ; Verhaege, Koen ; Bock, Karlheinz ; Roussel, Philippe J. ; Groeseneken, Guido ; Maes, Herman E.

Author_Institution

IMEC, Leuven, Belgium

fYear

1996

fDate

10-12 Sept. 1996

Firstpage

302

Lastpage

315

Abstract

The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching, the triggering of snapback and the CDM-specific bipolar saturation mode are addressed. The optimal gate length for CDM protection in advanced submicron technologies is discussed.

Keywords

CMOS integrated circuits; MOSFET; avalanche breakdown; capacitance; electrostatic discharge; equivalent circuits; integrated circuit modelling; protection; semiconductor device models; thermal analysis; transient analysis; CDM ESD stress; CDM protection; NMOSFET; advanced submicron technologies; avalanching; bipolar saturation mode; compact model; grounded-gate nMOS behaviour; n-channel device; optimal gate length; parasitic bipolar transistor; snapback triggering; thermal model; Avalanche breakdown; CMOS integrated circuits; CMOSFETs; Capacitance; Electrostatic discharges; Equivalent circuits; Integrated circuit modeling; Protection; Semiconductor device breakdown; Semiconductor device modeling; Semiconductor device thermal factors; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 1996. Proceedings

Print_ISBN

1-878303-69-4

Type

conf

DOI

10.1109/EOSESD.1996.865157

Filename

865157