Title :
IC reliability simulator ARET and its application in design-for-reliability
Author :
Xuan, Xiangdong ; Chatterjee, Abhijit ; Singh, Adit D. ; Kim, Namsoo P. ; Chisa, Mark T.
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
To accomplish effective IC reliability evaluation and design-for-reliability (DFR), a reliability, simulator ARET was developed at Georgia Tech. ARET simulates IC reliability at both component and system levels. It also handles the ICs with physical defects generated in fabrication by a statistical approach. ARET was verified by a series of stress tests conducted at The Boeing Company, which has shown a promising accuracy. In order to perform a practical DFR, another distinct feature - reliability hotspot identification was developed in ARET. By sensitivity analysis, it can determine the weakest components in the circuit under certain failure mechanisms, which allows a local design update to obtain an improved IC reliability. This makes DFR feasible by saving huge amount of work that needs to be performed in a complete VLSI circuit re-design for reliability.
Keywords :
circuit simulation; failure analysis; integrated circuit design; integrated circuit reliability; sensitivity analysis; ARET IC reliability simulator; DFR; IC reliability evaluation; VLSI circuit re-design for reliability; design-for-reliability; fabrication physical defects; failure analysis; reliability hotspot identification; sensitivity analysis; Application specific integrated circuits; Circuit simulation; Circuit testing; Electromigration; Fabrication; Failure analysis; Integrated circuit design; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit reliability; Sensitivity; Stress; Very large scale integration;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250775
