IC reliability simulator ARET and its application in design-for-reliability

To accomplish effective IC reliability evaluation and design-for-reliability (DFR), a reliability, simulator ARET was developed at Georgia Tech. ARET simulates IC reliability at both component and system levels. It also handles the ICs with physical defects generated in fabrication by a statistical approach. ARET was verified by a series of stress tests conducted at The Boeing Company, which has shown a promising accuracy. In order to perform a practical DFR, another distinct feature - reliability hotspot identification was developed in ARET. By sensitivity analysis, it can determine the weakest components in the circuit under certain failure mechanisms, which allows a local design update to obtain an improved IC reliability. This makes DFR feasible by saving huge amount of work that needs to be performed in a complete VLSI circuit re-design for reliability.