DocumentCode
2367209
Title
On estimation of fault efficiency for path delay faults
Author
Fukunaga, Masayasu ; Kajihara, Seiji ; Takeoka, Sadami
Author_Institution
Graduate Sch. of Comput. Sci. & Syst. Eng., Kyushu Inst. of Technol., Japan
fYear
2003
fDate
16-19 Nov. 2003
Firstpage
64
Lastpage
67
Abstract
In this paper, we propose a method to estimate fault efficiency for path delay faults based on untestable path analysis. In path delay fault testing, fault coverage of test patterns is usually, very low, because logic circuits often have huge number of paths including many untestable paths. Hence we should compute fault efficiency rather than fault coverage, but it is too difficult to compute exact fault efficiency in a short time, because there is no method to compute total number of untestable paths quickly. The proposed method statistically estimate the number of untestable paths based on untestable path analysis, and compute fault efficiency. Experimental results show that the proposed method can accurately estimate fault efficiency of given test patterns in a reasonable time.
Keywords
VLSI; automatic test pattern generation; combinational circuits; fault diagnosis; logic testing; sequential circuits; VLSI; benchmark circuits; combinational circuits; computation time; fault coverage; fault efficiency; full scan sequential circuits; logic circuits; path delay faults; single delay fault; test patterns; untestable path analysis; Circuit faults; Circuit testing; Combinational logic circuits; Delay effects; Delay estimation; Electrical fault detection; Fault detection; Fault diagnosis; Logic circuit testing; Logic testing; Manufacturing; Performance evaluation; Sequential logic circuits; Test pattern generators; Very-large-scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1951-2
Type
conf
DOI
10.1109/ATS.2003.1250784
Filename
1250784
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