Title :
Software-based delay fault testing of processor cores
Author :
Singh, Virendra ; Inoue, Michiko ; Saluja, Kewal K. ; Fujiwara, Hideo
Author_Institution :
Nara Inst. of Sci. & Technol., Japan
Abstract :
This paper presents a software-based self-testing methodology for delay fault testing. Delay faults affect the circuit functionality only when it can be activated in functional mode. A systematic approach or the generation of test vectors, which are applicable in functional mode, is presented. A graph theoretic model (represented by IE-Graph) is developed in order to model the datapath. A finite state machine model is used for the controller. These models are used for constraint extraction so that the generated test can be applied in functional mode.
Keywords :
automatic test pattern generation; built-in self test; fault diagnosis; finite state machines; microprocessor chips; constraint extraction; finite state machine model; functional mode; graph theoretic model; instruction execution graph; processor cores; software-based delay fault testing; software-based self-testing; test vectors; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Data mining; Delay; Electronic equipment testing; Fault diagnosis; Finite state machines; Microprocessors; Registers; Self-testing; Software testing;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250785
