A DFT approach for path delay faults in interconnected circuits

Author

Pomeranz, Irith ; Reddy, Sudhakar M.

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

72

Lastpage

75

Abstract

We propose a new DFT approach for path delay faults in interconnected circuits. The proposed approach places multiplexers on the interface between two circuits in order to create new testable paths through the interconnection. The new testable paths allow us to increase the number of paths tested in each circuit. This approach does not require interconnected circuits to be isolated by test wrappers.

Keywords

automatic test pattern generation; combinational circuits; design for testability; fault diagnosis; logic testing; multiplexing equipment; DFT approach; MCNC synthesis benchmarks; combinational logic; delay defects; inserting multiplexers; interconnected circuits; logical paths; matching paths; path delay faults; testable paths; Circuit faults; Circuit testing; Cities and towns; Combinational logic circuits; Delay effects; Design for testability; Electrical fault detection; Fault diagnosis; Hardware; Integrated circuit interconnections; Inverters; Logic circuit testing; Multiplexing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250786

Filename

1250786