• DocumentCode
    2367412
  • Title

    PLL based high speed functional testing

  • Author

    Jayabalan, Jayasanker ; Goh, Chee Kiang ; Leong, Ooi Ban ; Seng, Leong Mook ; Iyer, Mahadevan K. ; Tay, Andrew A O

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore
  • fYear
    2003
  • fDate
    16-19 Nov. 2003
  • Firstpage
    116
  • Lastpage
    119
  • Abstract
    A PLL based at-speed functional testing concept, which eliminates the need for a tester-driven high-speed clock interface is presented. Jitter tolerance circuits have been implemented to provide immunity, to clock jitter. The concept was verified on a 100 mm2 silicon device built in 0.18 μm technology, above 200 MHz speed. Simulation results show that the concept can be extended to higher speeds.
  • Keywords
    integrated circuit testing; logic testing; phase locked loops; timing jitter; 0.18 micron; 200 MHz; PLL based high speed functional testing; clock jitter immunity; high speed digital testing; jitter tolerance circuits; Circuit testing; Clocks; Frequency estimation; Frequency synchronization; Integrated circuit testing; Jitter; Logic circuit testing; Phase locked loops; Programmable control; Signal design; Signal processing; Uncertainty;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2003. ATS 2003. 12th Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-1951-2
  • Type

    conf

  • DOI
    10.1109/ATS.2003.1250794
  • Filename
    1250794
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2367412