DocumentCode :
2367430
Title :
Substrate deep depletion: an innovative design concept to improve the voltage rating of SOI power devices
Author :
Napoli, Ettore ; Udrea, Florin
Author_Institution :
Dept. of Electron. & Telecommun. Eng., Napoli Univ.
fYear :
2006
fDate :
4-8 June 2006
Firstpage :
1
Lastpage :
4
Abstract :
This paper, for the first time, proposes and experimentally demonstrates an innovative design concept for SOI power devices that exploits substrate deep depletion to considerably improve device voltage rating. This dynamic effect allows the design of a whole new generation of SOI power devices providing dramatically improved performances. Eligible applications are power conditioning circuits (flyback, resonant) in which the device sustains transient voltages higher than bus voltage. Numerical simulations explain the physics of the device. Experimental measurements on SOI power LDMOS using P- substrate clearly demonstrate that the newly proposed "deep depletion SOI device" presents 170V static breakdown voltage while sustains transient overvoltages up to 290V
Keywords :
power MOSFET; semiconductor device breakdown; silicon-on-insulator; 170 V; 290 V; P substrate; SOI power devices; deep depletion SOI device; innovative design concept; power LDMOS; power conditioning circuits; static breakdown; substrate deep depletion; voltage rating improvement; Breakdown voltage; Circuit testing; Design engineering; Power conditioning; Power engineering and energy; Resonance; Substrates; Surges; Switches; Switching circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on
Conference_Location :
Naples
Print_ISBN :
0-7803-9714-2
Type :
conf
DOI :
10.1109/ISPSD.2006.1666070
Filename :
1666070
Link To Document :
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