Title :
A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs
Author :
Narasimhan, Ashok ; Divekar, Shantanu ; Elakkumanan, Praveen ; Sridhar, Ramalingam
Author_Institution :
Dept. of Comput. Sci. & Eng., SUNY, Buffalo, NY, USA
Abstract :
Performance of system-on-chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz in voltage mode clock signaling. This work presents a reliable quasisynchronous clock distribution scheme for NoCs that uses a single-ended current-mode clock signaling technique. Simulation results show the circuit to be reliable under process variations, and having an average of 11% improvement in delay and average power over other current mode schemes. Simulation results indicate acceptable performance up to 7.5GHz in 0.18/μm technology.
Keywords :
delays; integrated circuit interconnections; microwave integrated circuits; noise; system buses; system-on-chip; timing; 0.18 micron; bus delays; bus noise; clock distribution network; current-mode clock distribution scheme; current-mode clock signaling technique; networks-on-chip; point-to-point interconnects; process variations; quasisynchronous clock distribution scheme; system-on-chips; voltage mode clock signaling; Circuit simulation; Clocks; Delay; Energy consumption; Frequency; Integrated circuit interconnections; Network-on-a-chip; Semiconductor device noise; Voltage; Wire;
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
Print_ISBN :
0-7695-2264-5
DOI :
10.1109/ICVD.2005.18
