High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Author

Lin, J.C. ; Chiou, W.C. ; Yang, K.F. ; Chang, H.B. ; Lin, Y.C. ; Liao, E.B. ; Hung, J.P. ; Lin, Y.L. ; Tsai, P.H. ; Shih, Y.C. ; Wu, T.J. ; Wu, W.J. ; Tsai, F.W. ; Huang, Y.H. ; Wang, T.Y. ; Yu, C.L. ; Chang, C.H. ; Chen, M.F. ; Hou, S.Y. ; Tung, C.H. ; J

Author_Institution

R&D, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan

fYear

2010

fDate

6-8 Dec. 2010

Abstract

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (μ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TV´s) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

Keywords

CMOS integrated circuits; integrated circuit reliability; nanoelectronics; semiconductor device reliability; three-dimensional integrated circuits; wiring; 3D IC technology; 3D integration scheme reliability; CMOS foundry technology; Si foundry technology; critical 3D integrated circuit enabling technology; high density 3D integration; high-density three dimensional chip integration structures; microbump process; redistribution layer; through silicon via; wafer thinning; wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4424-7418-5

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2010.5703277

Filename

5703277