Optimal scan tree construction with test vector modification for test compression

This paper presents a method to reduce test data volume and test application time for a full-scan circuit. The proposed method constructs a scan tree in which scan flip-flops are placed and routed in a tree structure. Although one scan input to the scan tree drives several scan chains with varying length, it is guaranteed that every test vector of a test set can be loaded into the scan tree. Since the height of the scan tree decides test data volume of the test set, the method modifies the test set so as to minimize the height. The procedure of test vector modification consists of don´t care identification for the test set and a solution to a vertex coloring problem for an incompatibility graph constructed from the test set including don´t cares. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce, on average, test data volume and test application time by 70%.