A RISC hardware platform for low power Java

Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of resources available in many embedded systems. Hardware support for Java is a potential solution, reducing memory and power requirements while increasing execution speed. This paper presents a prototype architecture for hardware Java support within a RISC processor core, along with a synthesised asynchronous implementation. A breakdown of gate and silicon level simulation results quantifies where performance increases are achieved, providing a template for future work.