DocumentCode
2367626
Title
Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding
Author
Chen, K.N. ; Shaw, T.M. ; Cabral, C., Jr. ; Zuo, G.
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2010
fDate
6-8 Dec. 2010
Abstract
We demonstrate a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding. Hybrid Cu-oxide hybrid bonding shows excellent bond quality and performances in terms of alignment, bond strength, and ambient permeation oxidation. Excellent performances of initial reliability and quality evaluations for Cu-oxide hybrid bonding are key milestones in proving manufacturability of 3D integration technology.
Keywords
oxidation; semiconductor device reliability; three-dimensional integrated circuits; wafer bonding; wafer-scale integration; 3D integration technology; Cu-oxide hybrid bonding; W TSV; bond quality; bond strength; hybrid wafer bonding; permeation oxidation; reliability; structural design; wafer-level 3D integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0163-1918
Print_ISBN
978-1-4424-7418-5
Electronic_ISBN
0163-1918
Type
conf
DOI
10.1109/IEDM.2010.5703283
Filename
5703283
Link To Document