Engineered substrates for future More Moore and More than Moore integrated devices

Author

Clavelier, L. ; Deguet, C. ; Di Cioccio, L. ; Augendre, E. ; Brugere, A. ; Gueguen, P. ; Le Tiec, Y. ; Moriceau, H. ; Rabarot, M. ; Signamarcheix, T. ; Widiez, J. ; Faynot, O. ; Andrieu, F. ; Weber, O. ; Le Royer, C. ; Batude, P. ; Hutin, L. ; Damlencourt

Author_Institution

CEA-LETI, MINATEC, Grenoble, France

fYear

2010

fDate

6-8 Dec. 2010

Abstract

In 1991, M. Bruel (1) invented and patented the Smart Cut technology to fabricate Silicon On Insulator (SOI) substrates. The process relies on the transfer of a high quality single crystal layer from one wafer to another: implantation of gaseous ions in a single crystal wafer, direct bonding on a stiffener and splitting (Fig 1). The invention of this SOI process combined with the entrepreneurship of SOITEC paved the way to high quality SOI substrates mass production. Today, SOI is a mature product (up to 300mm diameter) and now developments are focused on the integration of new materials and functionalities in order to improve device performances and enlarge the application spectrum.

Keywords

MOSFET; bonding processes; ion implantation; semiconductor device manufacture; silicon-on-insulator; substrates; Moore integrated devices; SOI process; SOI substrates mass production; SOITEC; Si; device performances; direct bonding; engineered substrates; entrepreneurship; gaseous ion implantation; high quality single crystal layer; silicon on insulator substrates; single crystal wafer; smart cut technology; splitting; stiffener;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4424-7418-5

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2010.5703285

Filename

5703285