DocumentCode
2367714
Title
Charge-recovery power clock generators for adiabatic logic circuits
Author
Arsalan, Muhammad ; Shams, Maitham
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fYear
2005
fDate
3-7 Jan. 2005
Firstpage
171
Lastpage
174
Abstract
To get maximum energy efficiency from adiabatic logic circuits several charge-recovery power clock generators (PCGs) have been published in recent years. This paper compares and analyzes the performance and energy efficiency of various PCGs in a uniform test environment. The test benches are laid out in a standard 0.18 μm CMOS technology and the results are mainly based on post layout simulations.
Keywords
CMOS logic circuits; circuit simulation; clocks; logic circuits; 0.18 micron; CMOS technology; adiabatic logic circuits; charge recovery; energy efficiency; post layout simulations; power clock generators; CMOS technology; Circuit simulation; Circuit testing; Clocks; Energy consumption; Energy efficiency; Logic circuits; Logic gates; Power dissipation; Power generation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2005. 18th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2264-5
Type
conf
DOI
10.1109/ICVD.2005.64
Filename
1383272
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