Issues in a submicron Cu interconnect system using liftoff patterning

A liftoff process has been used to study integration issues associated with submicron copper interconnects. Copper interconnects clad with upper and lower layers of chromium have been patterned at 0.8 and 0.5 μm dimensions using a silicon template-based tri-layer resist stack. Reliability studies have been performed which indicate that complete cladding of copper lines is necessary in integrated systems. To protect the interconnect sidewalls, blanket PECVD SiON films have been deposited over the lifted-off Cr/Cu/Cr structures. This type of sidewall cladding procedure has been found to be effective even when the lines are entrenched in polyimide layers. Based on these findings, 0.8 μm double level metal chains have been constructed with entrenched features, fully clad Cr/Cu/Cr interconnects, and lifted-off Ti/AlCu/Ti plugs