Issues on View Switching for RF SoC Verification

The main focus of this work is the functional verification of radio frequency systems on chip (RF SoCs). Different modeling approaches, like baseband modeling, analog modeling and event driven modeling, and their applications for verification are discussed. The possibilities and problems to use the Hierarchy Editor (HED) to switch between different modeling approaches on the fly in the top level schematic are discussed. Especially the cross domain connectivity issues between different model abstraction levels, like event driven modeling and analog modeling, are described in detail. Some suggestions for the circuit partitioning for verification purposes are given. This paper concludes with a suggestion for a possible extension of the Verilog HDL and the connect module insertion algorithm for the EDA industry.