• DocumentCode
    2367844
  • Title

    Layout guidelines for optimized ESD protection diodes

  • Author

    Bhatia, Karan ; Rosenbaum, Elyse

  • Author_Institution
    Univ. of Illinois at Urbana-Champaign, Urbana
  • fYear
    2007
  • fDate
    16-21 Sept. 2007
  • Abstract
    In this work, various layout options for ESD diodes´ PN junction geometry and metal routing are investigated. The current compression point (ICP) is introduced to define the maximum current handling capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the performance of the structures investigated herein.
  • Keywords
    circuit layout; electrostatic discharge; semiconductor diodes; PN junction geometry; current compression point; layout guidelines; maximum current handling capability; metal routing; optimized ESD protection diodes; Breakdown voltage; Circuits; Computational geometry; Degradation; Electrostatic discharge; Guidelines; Light emitting diodes; Parasitic capacitance; Protection; Routing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
  • Conference_Location
    Anaheim, CA
  • Print_ISBN
    978-1-58537-136-5
  • Type

    conf

  • DOI
    10.1109/EOSESD.2007.4401727
  • Filename
    4401727
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2367844