DocumentCode
2367864
Title
Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology
Author
Alvarez, David ; Chatty, Kiran ; Russ, Christian ; Abou-Khalil, Michel J. ; Li, Junjun ; Gauthier, Robert ; Esmark, Kai ; Halbach, Ralph ; Seguin, Christopher
Author_Institution
Infineon Technol., Essex Junction
fYear
2007
fDate
16-21 Sept. 2007
Abstract
Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.
Keywords
CMOS integrated circuits; MOSFET; electrostatic discharge; failure analysis; HBM failure; TLP failure; bulk CMOS technology; current crowding; design optimization; drain silicide region; drain silicide-blocking-to-gate spacing; failure analysis; gate-silicided ESD NMOSFET; size 45 nm; source silicide-blocking-to-gate spacing; Analytical models; CMOS technology; Design optimization; Electrostatic discharge; Failure analysis; MOSFETs; Proximity effect; Robustness; Silicides; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
Conference_Location
Anaheim, CA
Print_ISBN
978-1-58537-136-5
Type
conf
DOI
10.1109/EOSESD.2007.4401728
Filename
4401728
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