Comparison of open and resistive-open defect test conditions in SRAM address decoders

Author

Dilillo, Luigi ; Girard, Patrick ; Pravossoudovitch, Serge ; Virazel, Arnaud ; Borri, Simone

Author_Institution

Lab. d´´Informatique de Robotique et de Microelectronique de Montpellier, Univ. de Montpellier II, France

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

250

Lastpage

255

Abstract

This paper presents a comparative analysis of open (ADOF: Address Decoder Open Fault) and resistive open defects in address decoders of embedded-SRAMs. Such defects are the primary target of this study because they are notoriously hard-to-detect faults. In particular, we consider dynamic defects which may appear in the transistor parallel plane of address decoders. From this study, we show that test conditions required for ADOFs testing (sensitization and observation) can be partially used also for resistive open defect testing.

Keywords

SRAM chips; built-in self test; fault diagnosis; integrated circuit testing; BIST; March tests; NOR-based pre-decoder; SRAM address decoders; dynamic defects; embedded-SRAM; hard-to-detect faults; open defect test conditions; resistive-open defect test conditions; transistor parallel plane; Costs; Decoding; Delay; Energy consumption; Fault diagnosis; Government; Integrated circuit testing; Production systems; Random access memory; Robots; SRAM chips; Self-testing; Testing; Uniform resource locators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250818

Filename

1250818