DocumentCode
2367962
Title
Implementation of dual-direction SCR devices in analog CMOS process
Author
Vashchenko, V.A. ; Kuznetsov, V. ; Hopper, P.J.
Author_Institution
Nat. Semicond. Corp., Santa Clara
fYear
2007
fDate
16-21 Sept. 2007
Abstract
Implementation of the dual-direction SCRs in a 5 V analog CMOS process was studied using pulsed I-V measurements and numerical simulations. A positive feedback mechanism associated with a parasitic vertical PNP was found, discussed and further utilized to improve the SCR latch-up robustness. The 2kV HBM 200V MM ESD protection capabilities with the holding voltage exceeding 5V were demonstrated in the ESD cells with the footprint size smaller than 2100 sq. um.
Keywords
CMOS analogue integrated circuits; electrostatic discharge; feedback; numerical analysis; thyristors; ESD protection; analog CMOS process; dual-direction SCR devices; dual-direction silicon controlled rectifier device; numerical simulations; parasitic vertical PNP; positive feedback mechanism; Breakdown voltage; CMOS process; Diodes; Electrostatic discharge; Numerical simulation; Protection; Pulse measurements; Robustness; Switches; Thyristors;
fLanguage
English
Publisher
ieee
Conference_Titel
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
Conference_Location
Anaheim, CA
Print_ISBN
978-1-58537-136-5
Type
conf
DOI
10.1109/EOSESD.2007.4401734
Filename
4401734
Link To Document