Design of a Switch-Level Analog Model for Verilog

This paper describes a modeling extension to Verilog called "Switch-Level Analog." It is inspired by the switch-level transistor modeling facility of Verilog, but extends the value domain from Logic to Reals and is based on linear relationships between the currents of branches and the voltages of nodes, rather than the charge relationships of nodes of earlier switch-level models. This capability allows the modeling of many types of modern circuit blocks that exploit the current-source (saturation mode) and resistive (linear mode) properties of transistors. The model is implemented as a PLI library. Modeling examples and performance data are presented.