DocumentCode :
2368028
Title :
A VPI-based combinational IP core module-based mixed level serial fault simulation and test generation methodology
Author :
Riahi, Pedram A. ; Navabi, Zainalabedin ; Lombardi, Fabrizio
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
fYear :
2003
fDate :
16-19 Nov. 2003
Firstpage :
274
Lastpage :
277
Abstract :
In this paper we are presenting a test methodology for performing module-bused mixed level fault simulation and test generation on System-on-Chip (SOC) combinational Intellectual Property (IP) cores for which both a pre-synthesis behavioral description and a post-synthesis netlist is available but in an analyzer output intermediate format not readable by core integraters. We use the Verilog Procedural Interface (VPI) to access and perform serial fault simulation on a pre-compiled core available as a mixed behavioral structural level design. We also use VPI to prepare a testbench environment for performing random pattern test generation. The simulation time results of applying this VPI-based test methodology on ISCAS85 Verilog benchmarks are also presented and compared to the flat (non-mixed level) version the proposed VPI-based environment.
Keywords :
automatic test pattern generation; combinational circuits; embedded systems; fault simulation; hardware description languages; integrated circuit testing; logic testing; system-on-chip; ISCAS85 Verilog benchmarks; SOC combinational IP core; Verilog procedural interface; behavioral description; embedded design; mixed level fault simulation; module-bused simulation; random pattern test generation; test generation methodology; testbench environment; Combinational logic circuits; Hardware design languages; Integrated circuit testing; Logic circuit testing; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-1951-2
Type :
conf
DOI :
10.1109/ATS.2003.1250822
Filename :
1250822
Link To Document :
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