DocumentCode :
2368072
Title :
Mapping symmetric functions to hierarchical modules for path-delay fault testability
Author :
Rahaman, Hafizur ; Das, Debesh K. ; Bhattacharya, Bhargab B.
Author_Institution :
IIIT-C, WB Univ. of Technol., Kolkata, India
fYear :
2003
fDate :
16-19 Nov. 2003
Firstpage :
284
Lastpage :
289
Abstract :
A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design and uses only 2-input AND-OR gates. General symmetric functions are then realized following a unate decomposition method. The synthesis procedure guarantees complete and robust path-delay fault testability in the circuit. Experimental results on several symmetric functions reveal that the hardware cost of the proposed design is low, and the number of paths in the circuit is reduced significantly compared to those in earlier designs. Results on circuit area and delay for a few benchmark examples are also reported.
Keywords :
Boolean functions; design for testability; fault simulation; logic CAD; logic testing; modules; 2-input AND-OR gates; cellular module; digital summation threshold logic array; hierarchical modules; path-delay fault testability; recursive design; robust testability; symmetric functions mapping; totally symmetric Boolean functions; unate decomposition method; Benchmark testing; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Cost function; Delay; Design automation; Design for testability; Hardware; Logic arrays; Logic circuit testing; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-1951-2
Type :
conf
DOI :
10.1109/ATS.2003.1250824
Filename :
1250824
Link To Document :
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