DocumentCode
2368138
Title
Optimal system-on-chip test scheduling
Author
Larsson, Erik ; Fujiwara, Hideo
Author_Institution
Embedded Syst. Lab., Linkoping Univ., Sweden
fYear
2003
fDate
16-19 Nov. 2003
Firstpage
306
Lastpage
311
Abstract
In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of all existing preemptive scheduling algorithm to produce an optimal solution in linear time. We extend the algorithm to handle (1) test conflicts elite to interconnection tests and (2) cases when a test limits all optimal usage of the TAM by using reconfigurable core test wrappers. Our extensions preserve the production of all optimal solution in respect to test time and minimizes the number of wrapper configurations as well as the TAM usage at each core. which implicitly minimizes the TAM routing. Experiments with our implementation shows its efficiency in comparison with previous approaches.
Keywords
automatic test pattern generation; design for testability; integrated circuit testing; logic testing; system-on-chip; core-based systems; independent job scheduling; interconnection tests; linear time; optimal test scheduling; preemptive scheduling algorithm; reconfigurable core test wrappers; system-on-chip test; test access mechanism; test conflicts; Automatic testing; Bandwidth; Design for testability; Integrated circuit testing; Laboratories; Logic circuit testing; Logic testing; Processor scheduling; Routing; Scheduling algorithm; System testing; System-on-a-chip; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1951-2
Type
conf
DOI
10.1109/ATS.2003.1250828
Filename
1250828
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