Title :
Optimization of mixed logic circuits with application to a 64-bit static adder
Author :
Wan, Yuanzhong ; Shams, Maitham
Author_Institution :
Carleton Univ., Ottawa, Ont., Canada
Abstract :
In this paper, a CMOS logic delay optimization algorithm was used to find the optimal number of pass transistors to use for buffer insertion into a CPL chain. The result was then used as a guide during the design of a 64-bit high-speed static adder. Simulation results indicated a worst-case critical-path delay of 650 ps for a device based on TSMC 0.18 μm technology.
Keywords :
CMOS logic circuits; adders; circuit optimisation; delays; logic design; 0.18 micron; 64 bits; 650 ps; CMOS logic delay optimization; CPL chain; TSMC technology; buffer insertion; mixed logic circuits; pass transistors; static adder; Adders; CMOS digital integrated circuits; Capacitance; Delay; Design optimization; Inverters; Logic circuits; MOS devices; MOSFETs; Voltage;
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
Print_ISBN :
0-7695-2264-5
DOI :
10.1109/ICVD.2005.132
