Title :
An on-chip jitter measurement circuit for the PLL
Author :
Tsai, Chin-Cheng ; Lee, Chung-Len
Author_Institution :
Dept. of Electron. Eng., Nat. Chaio Tung Univ., Taipei, Taiwan
Abstract :
A simple built-on-chip PLL jitter measurement circuit, which utilizes the vernier delay line principle, transforms timing difference signals into digital words and has a self calibration capability to minimize the mismatched error caused by the process variation, is proposed and demonstrated.
Keywords :
calibration; delay lines; error analysis; integrated circuit measurement; jitter; phase locked loops; time measurement; built-on-chip PLL jitter measurement circuit; digital words; mismatched error minimization; process variation; self calibration capability; timing difference signal transformation; vernier delay line principle; Calibration; Circuits; Delay lines; Error analysis; Integrated circuit measurements; Jitter; Logic testing; Particle measurements; Phase locked loops; Propagation delay; Semiconductor device measurement; Signal resolution; Time measurement;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250832
