Title :
Characterization of ESD risks in an assembly process by using component-level CDM withstand voltage
Author :
Tamminen, Pasi ; Viheriäkoski, Toni
Author_Institution :
Nokia Corp., Tampere
Abstract :
An effective ESD protection program in electronics manufacturing requires adaptation of CDM withstand information to practical protection actions. Tested withstand voltages differ from the real world discharges, which depends on physical environment and device package. In this study, we will present a calculation method that can be used to assess CDM risks in placement processes.
Keywords :
assembling; electronics packaging; electrostatic discharge; printed circuits; ESD protection program; assembly process; charge device model; component-level CDM withstand voltage; device package; electronics manufacturing; Assembly; Electronics packaging; Electrostatic discharge; Manufacturing processes; Protection; Shape; Stress; Surface discharges; Testing; Voltage;
Conference_Titel :
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-136-5
DOI :
10.1109/EOSESD.2007.4401753
