Title :
High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture
Author :
Pillarisetty, R. ; Chu-Kung, B. ; Corcoran, S. ; Dewey, G. ; Kavalieros, J. ; Kennel, H. ; Kotlyar, R. ; Le, V. ; Lionberger, D. ; Metz, M. ; Mukherjee, N. ; Nah, J. ; Rachmady, W. ; Radosavljevic, M. ; Shah, U. ; Taft, S. ; Then, H. ; Zelick, N. ; Chau,
Author_Institution :
Technol. & Manuf. Group, Intel Corp., Hillsboro, OR, USA
Abstract :
In this article we demonstrate a Ge p-channel QWFET with scaled TOXE = 14.5Å and mobility of 770 cm2/V*s at ns =5×1012 cm-2 (charge density in the state-of-the-art Si transistor channel at Vcc = 0.5V). For thin TOXE <; 40 Å, this represents the highest hole mobility reported for any Ge device and is 4× higher than state-of-the-art strained silicon. The QWFET architecture achieves high mobility by incorporating biaxial strain and eliminating dopant impurity scattering. The thin TOXE was achieved using a Si cap and a low Dt transistor process, which has a low oxide interface Dit. Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer, allowing healthy subthreshold slope in Ge QWFET for the first time. The Ge QWFET achieves an intrinsic Gmsat which is 2× higher than the InSb p-channel QWFET [3]. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.
Keywords :
CMOS integrated circuits; field effect transistors; germanium; low-power electronics; quantum well devices; Ge; P-channel device; biaxial strain; dopant impurity scattering; low power III-V CMOS architecture; phosphorus junction layer; quantum well field effect transistor;
Conference_Titel :
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4424-7418-5
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2010.5703312