DocumentCode :
2368353
Title :
Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs
Author :
Das, Tejasvi ; Washburn, Clyde ; Mukund, P.R. ; Howard, Steve ; Paradis, Ken ; Jang, Jung-Geau ; Kolnik, Jan ; Burleson, Jeff
Author_Institution :
Dept. of Electr. Eng., Rochester Inst. of Technol., NY, USA
fYear :
2005
fDate :
3-7 Jan. 2005
Firstpage :
295
Lastpage :
300
Abstract :
In this paper, we present the impact of both process and dimensional scaling on input loss (S11) prediction of MOSFET´s at GHz frequencies. We study the distributed gate effect, the non-quasi static effect, and report a drop in the resistive component of S11 for larger fingered devices at high frequencies (> 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. The impact of oxide thickness on S11 in the same process and across two different processes is also presented. The study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI Logic´s 0.18 μm and 0.11 μm processes, across five different wafers.
Keywords :
CMOS integrated circuits; MOSFET; S-parameters; radiofrequency integrated circuits; semiconductor device models; 0.11 micron; 0.18 micron; LSI Logic; RF MOSFET; RF dimensioned transistors; dimensional scaling; distributed gate effect; input loss prediction; lumped model; nonquasi static effect; oxide thickness; process scaling; resistive component; technology scaling; CMOS process; CMOS technology; Circuit noise; Electrical resistance measurement; Frequency estimation; Large scale integration; MOS devices; MOSFETs; Radio frequency; Semiconductor device noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2264-5
Type :
conf
DOI :
10.1109/ICVD.2005.86
Filename :
1383291
Link To Document :
بازگشت