DocumentCode :
2368358
Title :
Testing delay faults in embedded CAMs
Author :
Du, Xiaogang ; Reddy, Sudhakar M. ; Rayhawk, Joseph ; Cheng, Wu-Tung
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear :
2003
fDate :
16-19 Nov. 2003
Firstpage :
378
Lastpage :
383
Abstract :
Critical paths are analyzed in a CAM and minimum test patterns are proposed to detect delay faults in a CAM. The test patterns derived are shown to be covered by the basic algorithm proposed earlier in (G. Giles et al, Proc. Int. Test Conf. p.471-474, 1985).
Keywords :
built-in self test; content-addressable storage; logic testing; at-speed testing; built-in self-test; content addressable memory; delay fault testing; delay faults; embedded CAM; memory BIST; stuck-at faults; test pattern minimization; Associative memories; Built-in self-test; CADCAM; Cams; Circuit faults; Circuit testing; Computer aided manufacturing; Delay; Fault detection; Logic circuit testing; Pattern analysis; Random access memory; Self-testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-1951-2
Type :
conf
DOI :
10.1109/ATS.2003.1250841
Filename :
1250841
Link To Document :
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