Cache coherence in a multiport memory environment

The effects of various cache coherence strategies are analyzed for a multiported shared memory multiprocessor. Analytical models for concurrent read exclusive write access (CREW) and concurrent read concurrent write access (CRCW) are developed including shared-not-cacheable, snooping bus, snooping bus with cache-to-cache transfers, and directory protocols. The performance of each protocol is shown as the hit rate, main memory-to-cache memory cycle time ratio, fraction of shared data, read percentage, and number of partitions are varied. Overall, results indicate that a snooping bus with cache-to-cache transfer scheme provides consistently fast access times over a wide range of execution parameters. However, nearly equivalent performance can be obtained with simpler directory based schemes. The implications of these results on increasing port complexity and memory usage are discussed