Title :
A BIST circuit for IDDQ tests
Author :
Hashizume, Masaki ; Takeda, Teppei ; Yotsuyanagi, Hiroyuki ; Tamesada, Takeomi ; Miura, Yukiya ; Kinoshita, Kozo
Author_Institution :
Tokushima Univ., Japan
Abstract :
In this paper, an IDDQ test time reduction method is proposed which is suitable for BIST approaches. Also, a BIST circuit for IDDQ tests, based on the method, is proposed. The layout of a CMOS logic circuit having the BIST circuit is designed and the performance is evaluated by SPICE simulation. The results show us that IDDQ test time can be reduced by using this test circuit.
Keywords :
CMOS logic circuits; built-in self test; integrated circuit design; integrated circuit testing; logic design; logic testing; BIST circuit; CMOS logic circuit; IDDQ tests; test time reduction method; Built-in self-test; CMOS logic circuits; CMOSFET logic devices; Circuit faults; Circuit testing; Current supplies; Integrated circuit design; Integrated circuit testing; Logic circuit testing; Logic design; Logic gates; Logic testing; Performance evaluation; SPICE; Self-testing; Switching circuits;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250843
