Design and Optimization of a Versatile 700 V SPIC Process Using a Fully Implanted Triple-well Technology

Author

Chen, Wanjun ; Zhang, Bo ; Li, Zehong ; Li, Zhaoji ; Deng, Xiaochuan ; Cheng, Jianbing

Author_Institution

Center of IC Design, Univ. of Electron. Sci. & Technol. of China, Sichuan

fYear

2006

fDate

4-8 June 2006

Firstpage

1

Lastpage

4

Abstract

A SPIC (smart power IC) process with a wide range of devices up to 700 V has been designed and optimized. An important feature is that all the devices have been realized by using a fully implanted triple-well technology in a P-type single crystal without epitaxial layer or buried layer. The results of this process are the low fabrication cost, simple process and small chip area. In addition to high voltage lateral DMOS (HV-LDMOS) transistor with the breakdown voltage (BV) 700 V as well as JFET device and low voltage CMOS (LV-CMOS) transistors have been fabricated using this process, a NPN type bipolar transistor is also realized and optimized by a additional implantation and drive-in. The major features of this process for SPIC fabrication have been clearly demonstrated

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit design; power integrated circuits; 700 V; JFET device; NPN type bipolar transistor; P-type single crystal; circuit optimization; fully implanted triple-well technology; high voltage lateral DMOS transistor; low voltage CMOS transistors; smart power IC process; versatile SPIC process; Boron; CMOS logic circuits; CMOS process; CMOS technology; Design optimization; Epitaxial layers; Fabrication; Isolation technology; Low voltage; Power integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on

Conference_Location

Naples

Print_ISBN

0-7803-9714-2

Type

conf

DOI

10.1109/ISPSD.2006.1666114

Filename

1666114