Designing multiple scan chains for systems-on-chip

We propose a branch-and-bound framework for designing non-reconfigurable multiple scan chains for systems-on-chip to minimize test application time. Multiple scan chain design problem defined in this paper involves (1) partitioning wrapper cells and core internal scan registers into multiple scan chains, and (2) ordering the wrapper cells and the registers in each scan chain. We design multiple scan chains with test application times within a few percentage of the corresponding optimal in practical run-times. We also demonstrate significant improvements in test application times over prior heuristics for designing multiple scan chains.