DocumentCode
2368541
Title
Test data volume reduction by test data realignment
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear
2003
fDate
16-19 Nov. 2003
Firstpage
434
Lastpage
439
Abstract
We explore an approach to input test data compression called realignment. Realignment changes a test sequence T consisting of n-bit vectors into a sequence T(m) consisting of m-bit vectors for m ≥ n. It then compresses T(m) instead of T to achieve larger levels of compression for T(m) than for T. By controlling m, realignment provides a range of possible solutions that differ in the data volume reduction and the amount of memory required between the decompressor and the circuit. The memory is required in order to translate m-bit vectors produced by the decompressor into n-bit vectors required by the circuit. We present experimental results to demonstrate this tradeoff for synchronous sequential circuits.
Keywords
VLSI; automatic test pattern generation; built-in self test; data compression; integrated circuit testing; logic testing; m-sequences; sequential circuits; buffer memory; input test data compression; m-bit vectors; n-bit vectors; synchronous sequential circuits; test data realignment; test data volume reduction; Circuit testing; Cities and towns; Combinational circuits; Costs; Data compression; Encoding; Integrated circuit testing; Logic circuit testing; Memory management; Self-testing; Sequential analysis; Sequential circuits; Sequential logic circuits; Test data compression; Very-large-scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1951-2
Type
conf
DOI
10.1109/ATS.2003.1250851
Filename
1250851
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