DocumentCode :
2368572
Title :
Investigating the CDM susceptibility of IC’s at package and wafer level by capacitive coupled TLP
Author :
Wolf, Heinrich ; Gieser, Horst ; Walter, Dirk
Author_Institution :
Fraunhofer-Inst. Zuverlassigkeit und Mikrointegration, Munich
fYear :
2007
fDate :
16-21 Sept. 2007
Abstract :
The method of the capacitive coupled transmission line pulsing (CC-TLP) is applied to a product IC at package level and for the first time at wafer level. The investigated product showed a field failure which could be reproduced by the CDM. The application of the CC-TLP to the product at package and wafer level also reproduced the field failure. Furthermore the measured failure currents correlate very well with the failure currents under CDM conditions.
Keywords :
capacitance; coupled transmission lines; semiconductor device models; CDM susceptibility; IC; capacitive coupled transmission line pulsing; package level; wafer level; Capacitance; Circuit testing; Current measurement; Electrostatic discharge; Integrated circuit packaging; Leakage current; Stress; Variable structure systems; Voltage; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-136-5
Type :
conf
DOI :
10.1109/EOSESD.2007.4401766
Filename :
4401766
Link To Document :
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