TCAD diagnosis of I/O-pin latchup in scaled-DRAM

Author

Tsuneno, Katsumi ; Sato, Hisako ; Narui, Seiji ; Masuda, Hiroo

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1996

fDate

2-4 Sept. 1996

Firstpage

153

Lastpage

154

Abstract

Summary form only given. This paper describes a TCAD analysis of I/O-pin latchup failure found in a shallow-well CMOS DRAM. The 0.35 μm DRAM I/O-pin showed significant degradation in latchup test of JEDEC Standard over-current stress. TCAD diagnosis of the failure was conducted and newly clarified the biasing effect of the guard-band (N⁺) layer and the layout-related latchup mechanism, which leads to a practical latchup-immunity design in sub-μm CMOS process and layout. To overcome process-margin problem against latchup, a simple CMOS process is proposed for the 0.35 μm DRAM.

Keywords

CMOS memory circuits; DRAM chips; buried layers; circuit CAD; computer aided analysis; electric breakdown; fault diagnosis; integrated circuit layout; integrated circuit modelling; 0.35 micron; I/O-pin latchup; JEDEC Standard over-current stress; TCAD diagnosis; latchup failure; latchup-immunity design; layout-related latchup mechanism; scaled-DRAM; shallow-well CMOS DRAM; submicron CMOS process; Breakdown voltage; CMOS process; Current measurement; Degradation; MOS devices; Optical buffering; Random access memory; Stress; Testing; Thyristors;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 1996. SISPAD 96. 1996 International Conference on

Print_ISBN

0-7803-2745-4

Type

conf

DOI

10.1109/SISPAD.1996.865317

Filename

865317