DocumentCode
2368677
Title
Analytical modeling of external latchup
Author
Farbiz, Farzan ; Rosenbaum, Elyse
Author_Institution
Illinois Univ., Urbana
fYear
2007
fDate
16-21 Sept. 2007
Abstract
A model is presented for external latchup. The effects of spacing, temperature, supply voltage and layout are captured in the model. The model shows a good fit to data in two different technologies, RF-CMOS and SmartMOS.
Keywords
CMOS integrated circuits; semiconductor device models; RF-CMOS; SmartMOS; analytical modeling; external latchup; Analytical models; Circuit testing; Diodes; Electronic mail; Electrostatic discharge; Ethernet networks; Semiconductor device modeling; Temperature; Variable structure systems; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
Conference_Location
Anaheim, CA
Print_ISBN
978-1-58537-136-5
Type
conf
DOI
10.1109/EOSESD.2007.4401772
Filename
4401772
Link To Document